Alexander Marquardt – Patents

Method and system for estimating the reliability of blacklists of botnet-infected computers

Versatile logic element and logic array block

  • US patent 7,218,133
  • Issued May 15, 2007 
  • See patent.

Routing Architecture For A Programmable Logic Device

  • US patent 6,970,014 
  • Issued Nov 29, 2005
  • See patent.

Alexander Marquardt Publications


Architecture and CAD for Deep Sub-Micron FPGAs


Cluster-Based Architecture, Timing-Driven Packing, and Timing-Driven Placement for FPGAs

Scientific Papers

The Stratix II Logic and Routing Architecture

The Stratix Routing and Logic Architecture

Speed and Area Trade-Offs in Cluster-Based FPGA Architectures

Timing-Driven Placement for FPGAs

Using Cluster Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density